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| a cdma power management system preliminary technical data ADP3500 features handles all cdma baseband and rf/if power management functions ldos optimized for specific cdma subsystems four backup ldos for stand-by mode operation four li-ion battery charge modes 5ma pre charge low current charge full current charge regulator mode (no current limit) ambient temperature: -30 cto+85 c 64pin 7x7 lqfp package applications cdma/cdma2000/pcs handsets general description the ADP3500 is a multifunction power system chip optimized for cdma cell phone power management. it contains 15 ldos. sophisticated controls are available for power up during battery charging, keypad interface, gpio/int function and rtc function. the battery charger has four modes as pre-charge, low current charge, full current charge, and regulator modes, and is designed for li-ion/li-polymer batteries. r e v. p r p 2 / 6 / 0 2 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or apatent rights of analog devices. reset output reset 32khz output control power on keypad i/f gpio serial i/f delay 10ms interrupt control ldo control battery charger reference ldo1 to 11 voltage detector analog block rtc counter stay-alive timer logic block ADP3500 figure 1. functional block diagram one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fa x : 781 / 326-87?3 ? a n a log d e v i c e s , i n c . , 200 2
rev.prp 2 /6/02 - 2 - ADP3500 - specifications main functions t a =-30 to +85 c, c vbat =1 f mlcc, vbat=3.6v unless otherwise noted. see table 2 for c out . parameter symbol conditions min typ max units shutdown gnd current power off ignd ldo3b : on, connect to rtcv through schottky diode. rtc/32k osc : active allotherldos:off all logic inputs : vbat or gnd mvbat: off 25 40 a operating gnd current stand-by mode operation (light load) stand-by mode operation (mid-load) active operation ignd ldo1b, 2b, 3b, 6b: on io=1ma for ldo1b & 3b io=300 a for ldo2b & 6b allotherldos:off rtc/32k osc: active mvbat: off all logic output: no load ldo1, 2, 3, 6, all sub-ldo: on, io=70% load allotherldos:off rtc/32k osc: active mvbat: on all logic outputs: no load ldo5: o ff all other ldos: on, 70% load rtc/32k osc: active all logic outputs: no load mvbat: on 60 275 650 125 a a a thermal shutdown threshold 160 c thermal shutdown hysteresis 35 c operational temperature range tope -30 +85 c adapter voltage range (recommendation) vadp 5.5 12 v vbat voltage range vbat 3.3 5.5 v ldo specifications t a =25 c, c vbat =1 f mlcc, vbat = vout+1v, nrcap=0.1 f. see table 2 for c out . baseband vdd main-ldo (ldo #1a) parameter symbol conditions min typ max units output voltage v ldo#1 io = 1 to 150 ma ta= -30 to +85 c 2.81 2.90 2.99 v output capacitor required for stability c ldo#1 2.2 f dropout voltage v do io = 150 ma 200 mv start-up time from shutdown 250 s gnd current i ldo#1 io = 150 ma 50 a baseband vdd sub-ldo (ldo #1b) parameter symbol conditions min typ max units output voltage v ldo#1b io = 1ma ta= -30 to +85 c 2.8 2.87 3.0 v gnd current i ldo#1b 10 a ADP3500 rev.prp 2 /6/02 - 3 - baseband avdd main-ldo (ldo #2a) parameter symbol conditions min typ max units output voltage v ldo#2 16 steps, 20mv/step, ta= 25c, io=50ma code : 1000 code : 0111 2.30 2.60 2.36 2.66 2.43 2.74 v v output default voltage v ldo#2 io=50ma,ta=25 c 2.46 2.52 2.6 v output voltage v ldo#2 16 steps, 20mv/step, io=50ma, ta= -30to+85 c code : 1000 code : 0111 2.29 2.57 2.36 2.66 2.47 2.81 v v output default voltage v ldo#2 io=50ma,ta=-30to+85 c 2.42 2.52 2.66 v output capacitor required for stability c ldo#2 1 f dropout voltage v do io = 50 ma 210 mv ripple rejection f = 1khz 50 db output noise voltage v noise f = 100 hz to 100 khz 120 v rms start-up time from shutdown 250 s gnd current i ldo#2 io = 50 ma 50 a baseband avdd sub-ldo (ldo #2b) parameter symbol conditions min typ max units output voltage v ldo#2b io = 300 a, v ldo#2a =2.6v ta= -30 to +85 c 2.50 2.70 v gnd current i ldo#2b 5 a refo switch parameter symbol conditions min typ max units on resistance r on ta= -30~+85 c, io=500 a 50 130 ? off leak i leak ldo2: on, switch: off 0.01 1 a coin cell main-ldo (ldo #3a) parameter symbol conditions min typ max units output voltage v ldo#3 io = 1 to 50 ma ta= -30 to +85 c 2.85 3.0 3.09 v dropout voltage v do io= 5 0 ma 140 mv output capacitor required for stability c ldo#3 1 f start-up time from shutdown 250 s gnd current i ldo#3 io = 50 ma 50 a coin cell sub-ldo (ldo #3b) parameter symbol conditions min typ max units output voltage v ldo#3b io=1ma ta= -30 to +85 c 2.85 2.97 3.15 v gnd current i ldo#3b 10 a audio ldo (ldo #4) parameter symbol conditions min typ max units output voltage v ldo#4 io = 1 to 180 ma ta=-30to+85 c 2.81 2.90 2.99 v output capacitor required for stability c ldo#4 2.2 f dropout voltage v do io = 180 ma 200 mv ripple rejection f = 1khz 50 db output noise voltage v noise f = 100 hz to 10 khz 50 v rms start-up time from shutdown 250 s gnd current i ldo#4 io = 180 ma 50 a ADP3500 rev.prp 2 /6/02 - 4 - vibrator ldo (ldo #5) parameter symbol conditions min typ max units output voltage v ldo#5 io = 1 to 150 ma ta= -30 to +85 c 2.75 2.9 3.05 v dropout voltage v do io = 150ma 200 mv output capacitor required for stability c ldo#5 2.2 f gnd current i ldo#5 io = 150 ma 50 a baseband core main-ldo (ldo #6a) parameter symbol conditions min typ max units output voltage v ldo#6 io = 1 to 50 ma ta= -30 to +85 c 2.52 2.60 2.68 v output capacitor required for stability c ldo#6 1 f dropout voltage v do io = 50 ma 160 mv start-up time from shutdown 250 s gnd current i ldo#6 io = 50 ma 50 a baseband core sub-ldo (ldo #6b) parameter symbol conditions min typ max units output voltage v ldo#6b io = 300 a ta= -30 to +85 c 2.5 2.57 2.7 v gnd current i ldo#6b 5 a rf rx1 ldo (ldo #7) parameter symbol conditions min typ max units output voltage v ldo#7 io = 1 to 100 ma ta= -30 to +85 c 2.81 2.9 2.99 v output capacitor required for stability c ldo#7 1.5 f dropout voltage v do io = 100 ma 200 mv ripple rejection f = 1khz 50 db output noise voltage v noise f = 100 hz to 100khz 40 v rms start-up time from shutdown 250 s gnd current i ldo#7 io=100ma 50 a rf tx ldo (ldo #8) parameter symbol conditions min typ max units output voltage v ldo#8 io = 1 to 150 ma ta= -30 to +85 c 2.81 2.9 2.99 v output capacitor required for stability c ldo#8 2.2 f dropout voltage v do io = 150ma 200 mv ripple rejection f = 1khz 50 db output noise voltage v noise f = 100 hz to 100khz 40 v rms start-up time from shutdown 250 s gnd current i ldo#8 io=150ma 50 a rf rx 2 ldo (ldo #9) parameter symbol conditions min typ max units output voltage v ldo#9 io = 1 to 50 ma ta= -30 to +85 c 2.81 2.9 2.99 v output capacitor required for stability c ldo#9 1 f dropout voltage v do io = 50ma 150 mv ripple rejection f = 1khz 50 db output noise voltage v noise f = 100 hz to 100khz 40 v rms start-up time from shutdown 250 s gnd current i ldo#9 io=50ma 5 0 a rf optional ldo (ldo #10) parameter symbol conditions min typ max units output voltage v ldo#10 io= 1 to 50 ma ta= -30 to +85 c 2.81 2.9 2.99 v ADP3500 rev.prp 2 /6/02 - 5 - output capacitor required for stability c ldo#10 1 f dropout voltage v do io = 50ma 150 mv ripple rejection f = 1khz 50 db output noise voltage v noise f = 100 hz to 100khz 40 v rms start-up time from shutdown 250 s gnd current i ldo#10 io=50ma 5 0 a optional ldo (ldo #11) parameter symbol conditions min typ max units output voltage v ldo#11 io = 1 to 100 ma ta= -30 to +85 c 1.42 1.5 1.58 v output capacitor required for stability c ldo#11 2.2 f ripple rejection f = 1khz 50 db output noise voltage v noise f = 100 hz to 100khz 50 v rms start-up time from shutdown 250 s gnd current i ldo#11 io=150ma 50 a voltage detector for ldo1 and ldo6 parameter symbol conditions min typ max units ldo1 detect voltage v det1 ta= -30 to +85 c 2.7 2.72 v ldo1 release voltage v det1 ta= -30 to +85 c 2.77 v ldo1 -nom v ldo1 hysteresis v hys1 ta= -30 to +85 c 35 52 85 mv ldo6 detect voltage v det6 ta= -30 to +85 c 2.3 2.33 v ldo6 release voltage v det6 ta= -30 to +85 c 2.40 v ldo6 -nom v ldo6 hysteresis v hys6 ta= -30 to +85 c 40 60 100 mv battery voltage divider: mvbat t a =-30 to 85 c, c vbat =10 f mlcc, c adapter =1 fmlcc unless otherwise noted parameter symbol conditions min typ max units mvbat output voltage 5 ? bit programmable v mvbat vbat=4.35v, mven = 1 code 10000 code 01111 2.484 2.673 2.508 2.697 2.533 2.727 v/v v/v mvbat output voltage step vstep vbat=4.35v, mven = 1 6 mv/lsb output drive current capability iout 1 2 ma mvbat load regulation ? vbat 0 < iout < 100 a 35mv mvbat output voltage step vbat = 4.35 v, mven = 1 6 mv operating battery current vbat = 4.35 v, mven = 1 65 85 a shutdown current vbat = 4.35 v, mven = 0 1 a battery charger t a =-30 to 85 c, c vbat =10 f mlcc, c adapter =1 f mlcc, 4.0v adapter 12v unless otherwise noted parameter symbol conditions min typ max units charger control voltage range 2 ? bit programmable vbat sense ta= 25 c, v r_sense = 6mv & 115mv, 5.5v adapter 12v (note 1) code 00 (default) code 01 code 10 code 11 3.926 4.150 4.170 4.190 3.980 4.190 4.210 4.230 4.034 4.230 4.250 4.270 v v v v charger control voltage range 2 ? bit programmable vbat sense ta= -20 to 55 c, v r_sense = 6mv & 115mv, 5.5v adapter 12v (note 1) code 00 (default) code 01 code 10 code 11 3.905 4.130 4.146 4.166 3.980 4.190 4.210 4.230 4.065 4.250 4.278 4.300 v v v v ADP3500 rev.prp 2 /6/02 - 6 - charger detect on threshold adapt er- vbat 110 165 225 mv charger detect off threshold adapt er- vbat 52350mv charger supply current i adapter adapter=5v, vbat=4.3v 2 ma current limit threshold high current limit (full charge current enabled) low current limit (full charge current disabled) adapt er-v isns adapter=5v vbat=3.6v vbat=3.0 v 135 40 160 55 185 70 mv mv pre-charge current source vbat ddlo 357ma base pin drive current note 2. 15 28 ma deep discharge lock-out (releasing voltage) ddlo vbat ADP3500 rev.prp 2 /6/02 - 8 - frequency jitter cycle to cycle >100cycles f jitter /s ec rtcv=3v, ta=25 c 40* 50* ns ns long term drift rtcv=3v, 3 minutes 10* ppm serial interface parameter min. typ. max units test condition/comments t cks 50 ns clk set-up time t css 50 ns cs set-up time t ckh 100 ns clk ?high? duration t ckl 100 ns clk ?low? duration t csh 100 ns cs hold time t csr 62 s cs recovery time t ds 50 ns input data set-up time t dh 40 ns input data hold time t rd 50 ns data output delay time t rz 50 ns data output floating time t csz 50 ns data output floating time after cs goes low. note: these parameters are not tested. absolute maximum ratings voltage on adapter pin to gnd ???????????..... -0.3, 15vmax voltage on vbat pin to gnd ?????????????? -0.3, 7vmax voltage on pin 6-13, 21-28 to gnd ???????????? -0.3, v ldo1 +0.3vmax voltage on pin 1, 62-64 ????????????????.. - 0.3, vbat+0.3v max voltage on pin 20, 32 ?????????????????.. - 0.3, v rtcv +0.3v max voltage on pin 60, 61 ?????????????????... - 0.3, v adapter +0.3v max voltage on pin 2-5, 14, 30, 31, 33 ?????????????. - 0.3, 7v max storage temperature range ???????????????. - 65 to +150 c operating temperature range ??????????????. - 30 to +85 c maximum junction temperature ?????????????. 125 c ja thermal impedance (lqfp-64) ????????????. 2 layer board 76 c/w ja thermal impedance (lqfp-64) ????????????. 4 layer board 54 c/w lead temperature range (soldering, 60sec) ????????... 300 c ordering guide model temperature range package ADP3500ast -30 c to 85 c lqfp 64 pins ADP3500 rev.prp 2 /6/02 - 9 - pin configuration o p t 2 - p w r o n k e y - o p t 1 - opt3 int- keypadcol0 keypadrow0 o s c i n o s c o u t 3 2 k o u t rstdelay- r e s e t + t e s t r t c v r e s e t i n - g p i o 3 g p i o 2 g p i o 1 g p i o 0 d a t a c l k i n c s refo ldo1 (baseband vdd) ldo2 (baseband avdd) ldo3 (rtc/coin-cell) ldo11 (option) ldo4 (audio) ldo6 (baseband core) ldo5 (vibrator) ldo7 (rf rx1) l d o 8 ( r f t x ) l d o 9 ( r f r x 2 ) l d o 1 0 ( r f o p t i o n ) a d a p t e r i s e n s e b a s e b v s a g n d b a t i d m v b a t n r c a p vbat blight tcxo_on dgnd r e s e t o u t - sleep- keypadcol1 keypadcol2 keypadcol3 keypadrow1 keypadrow2 keypadrow3 keypadrow4 keypadrow5 agnd a g n d a g n d v b a t vbat vbat vbat vbat 64 49 48 1 33 32 17 16 figure 2. pin configuration pin description pin mnemonic i/o supply function 1 opt3 i vbat optional power on input. ADP3500 will keep ?power on? during this pin goes ?high?. 2 keypadcol0 o ldo1 keypad column strobe 0 (open drain, pull low) 3 keypadcol1 o ldo1 keypad column strobe 1 (open drain, pull low) 4 keypadcol2 o ldo1 keypad column strobe 2 (open drain, pull low) 5 keypadcol3 o ldo1 keypad column strobe 3 (open drain, pull low) 6 keypadrow0 i ldo1 keypad row input 0. pulled up internally, 10k ? 7 keypadrow1 i ldo1 keypad row input 1. pulled up internally, 10k ? 8 keypadrow2 i ldo1 keypad row input 2. pulled up internally, 10k ? 9 keypadrow3 i ldo1 keypad row input 3. pulled up internally, 10k ? 10 keypadrow4 i ldo1 keypad row input 4. pulled up internally, 10k ? 11 keypadrow5 i ldo1 keypad row input 5. pulled up internally, 10k ? 12 tcxo_on i ldo1 logic input pin for main ldos (ldo1, ldo2, ldo3, ldo6) turning on control. l: off, h : on 13 sleep- i ldo1 logic input pin for rf rx ldos (ldo7 and ldo9). gating register data with this input for these ldos. ldo7 and ldo9 are turned off when sleep- goes low even if the registers set to on. 14 blight o vbat led drive. open drain output. 15 dgnd - - digital ground 16 int- o ldo1 interrupt signal output 17 rtcv - - supply input for rtc, 32khz osc, and some other logics. connects to coin cell battery in typical operation. 18 oscout - rtcv connect to 32.768khz crystal. 19 agnd - - analog ground 20 oscin - rtcv connect to 32.768khz crystal. 21 gpio0 i/o ldo1 general purpose input and output port. integrated interrupt function. interrupt occurs both falling and raising edge. 22 gpio1 i/o ldo1 general purpose input and output port. integrated interrupt function. interrupt occurs both falling and raising edge. 23 gpio2 i/o ldo1 general purpose input and output port. integrated interrupt function. interrupt occurs both falling and raising edge. 24 gpio3 i/o ldo1 general purpose input and output port. integrated interrupt function. interrupt occurs both falling and raising edge. 25 data i/o ldo1 serial interface data input and output. 26 cs i ldo1 serial interface chip select input. active high input. 27 clkin i ldo1 serial interface clock input. 28 resetin- i ldo1 reset input signal for internal reset signal and starts stay-alive timer. 29 32kout o rtcv 32.768khz output. output after 30ms when reset is released. ADP3500 rev.prp 2 /6/02 - 10 - 30 reset+ o rtcv reset output. invert signal of resetout-. open drain and low off leak. 31 resetout- o rtcv reset output. follows voltage detector operation. open drain output. 32 test i rtcv test pin. if the pin tied to rtcv, test mode runs. connect to gnd for normal operation. 33 rstdelay- o rtcv reset output. 50ms delayed. connect to baseband? reset input as typical application. open drain output. 34 vbat - - supply input. connect to battery. 35 ldo11 o vbat regulator #11 output. use for optional circuit. 36 ldo1 o vbat regulator #1 output. use for baseband i/o supply. 37 vbat - - supply input. connect to battery. 38 ldo3 o vbat regulator #3 output. if vbat>2.7v, the output is always active. use for coin cell supply. 39 agnd - - analog ground 40 refo o vbat output of ldo2 through fet switch. 41 ldo2 o vbat regulator #2 output. use for baseband analog supply. 42 vbat - - supply input. connect to battery. 43 ldo4 o vbat regulator #4 output. use for general analog supplies. ex. speaker amp. 44 ldo5 o vbat regulator #5 output. use for vibrator. 45 vbat - - supply input. connect to battery. 46 ldo6 o vbat regulator #6 output. use for baseband core supply. 47 ldo7 o vbat regulator #7 output. use for rf rx ic supply. gated with sleep- signal input. 48 vbat - - supply input. connect to battery. 49 ldo8 o vbat regulator #8 output. use for rf tx ic supply. 50 agnd - - analog ground 51 ldo9 o vbat regulator #9 output. use for rf rx ic supply. gated with sleep- input signal. 52 vbat - - supply input. connect to battery. 53 ldo10 o vbat regulator #10 output. use for optional circuit. 54 bvs - - battery voltage sense input for charger. connect to battery. 55 nrcap o vbat noise reduction capacitor. 0.1 f mlcc. 56 agnd - - analog ground 57 mvbat o vbat battery voltage divider output. buffered internally. connect to baseband adc. 58 base o adapter base drive output for pnp pass transistor 59 adapter - - ac adapter input. use to charger supply. 60 batid i adapter battery identification. 100k ? pulled up internally. ?l?: battery exist, ?h?: no battery. if batid=?h?, charger operates with ?no current limit?. 61 isense i adapter charge current sense input 62 pwronkey- i vbat power on/off key input. pulled up internally (140k ? ). 63 opt1- i vbat optional power on input. ADP3500 will keep ?power on? during this pin goes ?low?. 64 opt2- i/o vbat optional power on input. ADP3500 will keep ?power on? during this pin goes ?low?. while the part is powered up, the input is pulled to low (gnd) internally. don?t connect to any supply or signal source. ADP3500 rev.prp 2 /6/02 - 11 - block diagram serial i/f lpf opt2- pwronkey- opt1- opt3 int- keypadcol0 keypadrow0 6 osc in osc o ut 32k out vbat charger_detect delay 10ms data in 32khz delay 30ms rtc /clock stay/alive timer 0.25-8sec clks data delay 50ms rstdelay- reset+ test rtcv dgnd dgnd resetin- gpio3 gpio2 gpio1 gpio0 data clkin cs refo voltage detector ldo1 (baseband vdd) ldo2 (baseband avdd) ldo3 (rtc/coin-cell) ldo11 (option) ldo4 (audio) ldo6 (baseband core) ldo5 (vibrator) ldo7 (rf rx1) ldo8 (rf tx) ldo9 (rf rx2) ldo10 (rf option) adapter isense battery charger base bvs agnd batid mvbat (vbat measure) ref nrcap vbat charger control pwroff int rtc alarm key pad i/f 4 gpio + int blight ldo1 ldo2 ldo3 ldo6 ldo11 ldo4 ldo5 ldo7 ldo8 ldo9 ldo10 on/off logic on/off logic on/off logic on/off logic main sub main sub main main sub tcxo_on dgnd rtcv resetout- voltage_detect clk resetin_n data open drain batid ddlo ldo_en sleep- gpio_int / g pi_intrst data data poweron_n opt1_n opt2_n opt3 int_n power_on clks 5 sync 5 ldo1 ldo1 level trans 30 31 33 32 17 13 12 28 ref ldo1 level trans 35 53 51 49 47 44 43 46 38 41 36 55 40 57 60 54 58 61 59 34 37 42 45 48 52 19 39 50 56 62 63 64 1 16 3 4 5 6 7 8 9 10 11 2 level trans ldo1 14 keypadcol1 keypadcol2 keypadcol3 keypadrow1 keypadrow2 keypadrow3 keypadrow4 keypadrow5 15 26 27 25 21 22 23 24 20 18 29 ldo1 rtcv level translator level trans level trans clk 140k ? 100k ? level translator vbat & rtcv figure 3. overall block diagram ADP3500 rev.prp 2 /6/02 - 12 - theory of ope r ations as illustrated in figure 1 at the beginning, ADP3500 can be divided into two high level blocks ? analog and logic .theanalog block mainly consists of ldo regulators, battery charger, reference voltage, and voltage detector sub-blocks, all of which are powered by the main power source(vbat), namely the main battery or the charging adapter. on the other hand, the logic block is more complicated. all the logic sub-blocks are also powered by vbat except the rtc counter, 32mhz output control, reset output, and stay-alive timer. these sub-blocks are powered from rtcv pin, as indicated in figure 4 in shaded area. [vbat] 5 4 3 2 1 power on keypad i/f gpio serial i/f reset [rtcv]- rtc block 10 32k output control reset output 9 11 rtc c ounter stay-alive timer ldo control interrupt control delay 10ms 6 7 8 analog block figure 4. power partitioning of sub-blocks 1. analog blocks 1.1 low drop-out(ldo) regulators there are total four sub-ldos for each ldo1, 2, 3, and 6, in order to meet lower power consumption at light load (stand-by operation). they are used at low load condition, but they are continuously on even if the each main-ldos are on. the ldo3 and 3b are used for coin cell and ldo3b is always on until main battery (vbat) is downed to 2.5v due to ddlo function. ldo7 and 9 are controlled with sleep- signal. for detail of ldo on/off control, please refer to section ?2.8 ldo control?. table 1. ground currents of ldos with each handset operations. ldo names baseband vdd baseband core coin cell audio vibrator baseband avdd rf rx1 rf tx rf rx2 rf option option main ref total ldo ignd ldo # 1 6 3 4 5 2 7 8 9 10 11 power off off o ff 10 a off o ff off o ff off o ff off o ff 20 a30 a light load 10 a5 a10 a off o ff 5 a off o ff off o ff off 20 a50 a mid-load 60 a55 a60 a off o ff 55 a off o ff off 50 a off 20 a 300 a stand- by mode active load 60 a55 a60 a off o ff 55 a50 a50 a50 a50 a off 20 a 450 a talk 60 a55 a60 a50 a off 55 a50 a50 a50 a50 a50 a20 a 550 a ring 60 a55 a60 a50 a50 a55 a50 a50 a50 a50 a50 a20 a 600 a ADP3500 rev.prp 2 /6/02 - 13 - table 2. ldo operation overview regulator names current rating (ma) voltage (typ) or range program steps step size (mv) default cout ldo1a baseband vdd 150 2.90v n/a n/a - 2.2 f ldo1b baseband vdd sub 1 2.87v n/a n/a - 2.2 f ldo2a baseband avdd 50 2.36v~2.66v 16 20 2.52v 1 f ldo2b baseband avdd sub 0.3 2.33v~2.63v 16 20 2.49v 1 f ldo3a rtc/coin cell 50 3.0v n /a n/a - 1 f ldo3b rtc/coin cell sub 1 2.97v n/a n/a - 1 f ldo4 audio 180 2.9v n/a n/a - 2.2 f ldo5 vibrator 150 2.9v n/a n/a - 2.2 f ldo6a baseband core 50 2.6v n/a n/a - 1 f ldo6b baseband core sub 0.3 2.57v n/a n/a - 1 f ldo7 rf rx1 100 2.9v n/a n/a - 2.2 f ldo8 rf tx 150 2.9v n/a n/a - 2.2 f ldo9 rf rx2 50 2.9v n/a n/a - 1 f ldo10 rf option 50 2.9v n/a n/a - 1 f ldo11 option 100 1.5v n/a n/a - 2.2 f 1.2 battery charger 1.2.1. block diagram logic block isense adapter base gm en bvs batid charger_ detect batid gm ref pre-charge 5m a chv 0/1 bvs mven mv4:0 rsense ac adapter cvbat chi chen en ddlo ldo_ en + v(isense) - en en mvbat mvbat vbat 100k ? battery c adapter figure 5. battery charger block diagram ADP3500 rev.prp 2 /6/02 - 14 - 1.2.2. flow chart n y battery charger start v adapter >vbat ? set charger detect flag pre-charge 5ma vbat>ddlo ? batid=0 ? batid=0: battery connected batid=1: battery disconnected determined by external sense resistor set low current charge i adapter =250ma (50mv on rsense) pre-charge: off current loop disabled voltage loop regulates vbat to 4.0v pre-charge: off voltage detector vldo6>2.5v and vldo1>2.7v ? ldo1,1b,2,2b,3,6,6b voltage detector all enabled ldo3b: on ddlo comparator will operate if vbat>2v. even if vbat<2v, pre- charge is continuously applying 5ma. resetin- should be asserted until baseband chip active. then, chen=1 as default. figure 6. charger flow chart a ADP3500 rev.prp 2 /6/02 - 15 - reset sequence runs a baseband sets charge voltage baseband sets mvbat gain baseband enables full charge current? (chi=1?) n y low current charge: off setfullcurrentcharge i adapter =750ma (150mv on rsense) baseband chen=0? n y charging terminated chi=0: full current charge off chi=1: full current charge on figure 7. charger flow chart b 1.2.3. charger detect function the ADP3500 will detect that a charging adapter has been applied when the voltage at the adapter pin exceeds the voltage at batsns. the adapter pin voltage must exceed the bvs voltage by a small positive offset. this offset has hysteresis to prevent jitter at the detection threshold. the charger detection comparator will set the charger_detect flag in the 20h register and generate an interrupt to the system. if the adapter input voltage drops below the detection threshold, charging will stop automatically and the charger_detect flag will be cleared and generate an interrupt also. 1.2.4. ddlo function and operation the ADP3500 contains a comparator that will lock out system operation if the battery voltage drops to the point of deep discharge. when the battery voltage exceeds 2.675 v, the reference will start as will the sub-ldo 3b. if the battery voltage drops below the hysteresis level, the reference and ldo's will be shut down, if for some reason they are still active. since ldo1 will be in deep dropout and well below the voltage detector threshold at this point, the reset generator will have already shut down the rest of the system via reset+, resetout-, and rstdelay-. if a charging adapter has been applied to the system, the ddlo comparator will force the charging current to trickle charge if the battery is below the ddlo threshold. during this time, the charging current is limited to 5 ma. when the battery voltage exceeds the upper threshold, the low current charging is enabled, which allows 55 mv (typical) across the external charge current sense resistor. see also figure 6, the battery charger flowchart. 1.3 mvbat the ADP3500 provides a scaled buffered output voltage for use in reading the battery voltage with an a/d converter. the battery voltage is divided down to be nominally 2.600 v at full scale battery of 4.35 v. to assist with calibrating out system errors in the ADP3500 rev.prp 2 /6/02 - 16 - ADP3500 and the external a/d converter, this full scale voltage may be trimmed digitally with 5 bits stored in register 12h. at full scale input voltage, the output voltage of mvbat can be scaled in 6 mv steps, allowing a very fine calibration of the battery voltage measurement. the mvbat buffer is enabled by the mven bit of register 11h, and will consume less than 1 ua of leakage current when disabled. 1.4 reference the ADP3500 has an internal, temperature compensated and trimmed band-gap reference. the battery charger and ldo's all use this system reference. this reference is not available for use externally. however, to reduce thermal noise in the ldos, the reference voltage is brought out to the nrcap pin through a 50kohm internal resistor. a cap on the nrcap pin will complete a low pass filter that will reduce the noise on the reference voltage. all the ldo's, with the exception of ldo3, use the filtered reference. since the reference voltage appears at nrcap through a 50kohm series internal impedance, it is very important to never place any load current on this pin. even a volt meter with 10 megohm input impedance will affect the resulting reference voltage by about 6 or 7 mv, affecting the accuracy of the ldo's and charger. if for some reason the reference must be measured, be certain to use a high impedance range on the volt meter or a discrete high impedance buffer prior to the measurement system. 2. logic blocks ADP3500 has following logic functions. ? three wire serial interface (cs, clk, data) ? rtc counter section has year, month, day, week, hour, minute, and second, and controls leap year, and days in month automatically. ? detect alarms based on rtc counter. ? periodically constant interrupt feature. (2hz, 1hz, 1/60hz, 1/3600hz, once a months) ? gpio and int ports control ? key-pad interface ? led light control ? ldo functions ? clock and reset output control ? stay-alive timer following is a block diagram based on logic circuit. ADP3500 rev.prp 2 /6/02 - 17 - cs clkin data keypadrow keypadcol gpio[3:0] resetin_n 32k osc oscin oscout rstdelay_n resetout_n reset pwronkey_n opt2_n opt3 chager_detect voltage_detect rtc_clk32k int_n delay 10ms keypad_int test 4 4 6 c t f g _ i n t clk32k voltage detect_delay power_on tcxo_on test_mode [vbat] write_data[7:0] write_enable sp_addr[4:0] clk512 sleep_n test_ldoenable blight dgnd batid analog blocks ldo control register pwronkey_n_sync, opt1_n_sync, opt3_sync interrupt register block led control analog block key pad i/f bl gpio opt1_n a l a r m _ i n t serial i/f data select resetin_n (reset for registers) rtc_resetin_n analog block r t c _ w r i t e _ e n a b l e r t c _ w r i t e _ d a t a [ 7 : 0 ] r t c _ s p _ a d d r [ 5 : 0 ] r t c _ r e a d _ d a t a [ 7 : 0 ] ldo control 32k clk output control 32k out t e s t m o d e c o n t r o l s i g n a l t i m i n g s i g n a l s rtc register block clk1k rtc_voltage_detect rtc_voltage_detect [rtcv] reset output control sync. t e s t _ v d e t _ s i g n a l r t c _ c s rtc output data select address decode test mode register block stay-alive timer data in power off int control register (reset & mask) key pad i/f control gpio control analog control registers rtc_test sync. sync. figure 8. l ogic block diagram 2.1 reset 2.1.1 resetin- signal the internal reset function is activated by external reset input, resetin-, and this is an asynchronous signal. the internal reset signal is used in the following blocks. ? serial i/f ? interrupt control ? stay-alive timer ? registers (refer to the register section for detail). ldos, controlled by serial i/f, are applied ?reset? by resetin-. ldo4, ldo5, ldo7, ldo8, ldo9, ldo10, ldo11 and ref0 are set to ?0?. in c ase resetin- has noise, the internal c ircuit may be in reset and cause the system unexpected result. please take enough treatment. resetin- is level translated from ldo1 to both vbat and rtcv supplies. ADP3500 rev.prp 2 /6/02 - 18 - 2.1.2 reset output control and 32khz output control using voltage detect signal, device generates 32k out, rstdelay-, resetout-, and reset signals. about 32ms after rtc_voltage_detect (voltage detect signal in rtcv supply) signal goes from ?0? to ?1?, 32k out signal is generated from internal rtc_clk32k signal. rstdelay_n (rstdelay-) goes to ?0? when rtc_voltage_detect is ?0?, and it goes to ?1? at 50ms after the ?0? to ?1? transition of rtc_voltage_detect. resetout_n (resetout-) and reset toggle their states. signal clk512 is a 512hz, which generated in usec counter block. 2.2 serial interface serial i/f write timing clkin cs t cks t css t ckh t ckl serial data t csr t csh addr5 addr4 0 ctrl1 (w) ctrl2 (w) data7 1 data0 serial i/f read timing single mode clkin cs t cks t css t ckh t ckl serial data t csr addr5 addr4 0 ctrl1 (r) ctrl2 (r) data7 1 data0 t rd t csz serial i/f read timing continuous mode clkin cs t cks t css t ckh t ckl serial data addr5 addr4 0 ctrl1 (r) ctrl2 (r) data7 1 t rd data0 addr5 t rz addr4 figure 9. serial interface signal table 3. set up and hold specifications parameter min. typ. max units test condition/comments ADP3500 rev.prp 2 /6/02 - 19 - t cks 200 ns clk set-up time t css 400 ns cs set-up time t ckh 400 ns clk ?high? duration t ckl 400 ns clk ?low? duration t csh 500 ns cs hold time t csr 62 s cs recovery time t ds 200 ns input data set-up time t dh 200 ns input data hold time t rd 300 ns data output delay time t rz 300 ns data output floating time t csz 300 ns data output floating time after cs goes low. 2.2.1. function block ADP3500 integrates the serial bus interface for easy communication with the system. the data bus consists of three wires, clk, cs, and data, and is capable of serial to parallel / parallel to serial conversion of data, as well as clock transfer. serial to parallel conversion parallel to serial conversion creation of write d ata sp_data [7:0] write_enable sp_addr [5:0] ps_data [7:0] synchlonization and data selection data rw_sel resetin_n cs clkin datain figure 10. serial interface block diagram serial interface block works during the time period at cs signal enable. after the falling edge of clkin signal right after the rising edge of cs signal, address, transfer control signal and write data are held in sequentially. in case data read, each of data will be prepared by rising edge of clkin and baseband chip may want to r ead or latch the data at falling edge of clkin. while cs is not asserted, clkin is ignored. if cs goes ?l? while clkin is continuously applied or input data, all data is canceled and data line would be high impedance. in this case, user needs to input the data again. please note that clkin should be stayed ?l? when cs goes h. rtc counter registers should be accessed at a certain time (>62 s) later after cs assertion. asserting resetin_n (resetin-) signal resets the block.. notes: ? clkin=10khz to 1mhz, 20/80% duty cycle. ? clkin should be ?l? when cs goes ?h?. ? in case of rtc counter access, the access should be approximately 62 s, (2 clock cycles of clk32k) after the cs signal is asserted, to hold the rtc value. ? the cs should not be asserted for 62 s, (2 clock cycles of clk32k) after the cs is released. ? cs signal should never be asserted for 1 sec or longer, otherwise rtc counter makes error. 2.2.2 data input/output timing address(6bit) r/w(2bit) read data(8bit) 4 3 2 1 0 5 1 0 7 6 5 4 3 2 1 0 ADP3500 rev.prp 2 /6/02 - 20 - figure 11. serial i/f data read/write timing sp_addr[5:0] : 6bit address sp_ctrl[1:0] : 2bit read/write control (01: write, 10: read) sp_data[7:0] : 8bit input/output data * all transfer will be done msb first. 2.3 g pio+int gpio block has 4 channel i/o function and interrupt. with gpio control register (1ah), it is possible to control input or output setting of each channel individually. the output data is set in gpio register (1ch). when the port is set as input mode, the input signal transition from ?1? to ?0? and from ?0? to ?1?, then generate interrupt signal with edge detection. the held interrupt signals are reset by gpio int reset register (1dh). setting gpio mask register (1bh) to ?1? enables the interrupt of gpio. (not masked, ?1? at default in reset.) 2.4 int register in case the interrupt event has occurred, ?1?, the signal is held in this register. int detect and reset are synchronized at the rising edge of clk32k. in case the interrupt event and reset signal are occurred at same time, interrupt event has priority. resetin_n signal resets int register (1eh) to ?0? (no int detected), except alarm_int and ctfg_int. int mask register (1fh) to ?1? (not masked). this block masks alarm_int and ctfg_int, which generated in rtcv block, but these signals are reset with alarm control register (0dh) and ctfg control register (0eh). the interrupt signal, int_n, is an ?inverted or? signal of value in int register and gpio register. data-in register is a port to read an interrupt status. the input data are through sync block except alarm signal. since this is for just read back purpose, user cannot write any data. batid rtc alarm charger_detect opt3 opt1- pwronkey- sync block data_in registor (addr: 20h) register figure 12. data-in block 2.5 keypad control & led drive keypadcol[3:0] are open drain output. the keypadrow[5:0] are falling edge trigger input (input state transition from ?1? to ?0?) and generate interrupt signal, and are pulled up to ldo1. by providing 4 keypad-column outputs and 6 keypad- row inputs the ADP3500 can monitor up to 24 keys with baseband chip. writing column outputs and reading row inputs are controlled through serial interface. the address of the keypadrow is 19h, and keypadcol is 18h. initial register value is ?0? that means an output of keypadcol is ?high impedance?. back-light drive is an open drain output. maximum current of internal fet is 100ma. initial register value is ?0? that means the output of blight is ?high impedance?. ADP3500 rev.prp 2 /6/02 - 21 - 2.6 power on input pwronkey and opt1 have pull-up resistors, and others are not. in addition to these inputs, other internal input signals such as charger_detect and alarm signal (alarm_int) from rtc enable main and sub ldos of ldo1, 2, 3 and ldo6. power on status is hold by a latch data in delay circuit, called voltage_detect_delay (please see 4.8 for more detail). opt3 has a lower voltage threshold. opt2 is different structure to the other inputs, and is pulled down to zero by internal signal when phone is power on status, in order to make sure to have power on status even if short-term disconnection is happened. following is a block diagram and power on sequence. vbat voltage_detect_delay charger_detect alarm_int power_on pwronkey- opt1- opt2- opt3 140k ? 140k ? int block figure 13. power on input block diagram ? voltage_detect_delay : voltage detect signal (10ms delay) (1: assert) ? charger_detect : charger detect signal (1: assert) ? alarm_int : alarm detect signal (alarm 1 or 2) (1: assert) ? pwronkey- : power on key input (0: assert) ? opt1- : power on signal (0: assert) ? opt2- : power on signal (0: assert) ? opt3 : power on signal (1: assert) ADP3500 rev.prp 2 /6/02 - 22 - poweronkey poweron ldo1,2,3,6 ldo1b, 2b, 6b voltage detector voltage_detect_delay rstdelay- opt2 int- serial i/f 10ms 50ms power on power off clear int- and set pwroff(21h)=1 clear int- figure 14. power on sequence 2.7 10 milisecond delay this block generates a 10ms delayed signal after the reset of the voltage_detect signal is released. after 10ms (11 clocks of 1024hz) since the voltage_detect signal is asserted, the voltage_detect_delay signal is asserted. if the duration of the voltage_detect signal is less than 10ms, voltage_detect_delay signal will not be asserted. when the voltage_detect signal is released, the voltage_detect_delay signal is also released simultaneously. the voltage_detect_delay signal can be reset with writing ?1? in power off register (21h). * user just need to write ?1? in the power off register to reset voltage_detect _delay, and not need to over-write it with ?0?. 2.8 ldo control the ldo control block controls power on/off of ldo block. the function in this block has: ? hardware control using external signals ? software control using serial interface ? mixture of hardware and software above ldo1, ldo2, ldo3, and ldo6 are structured with main and sub ldos. ldo4, ldo5, ldo7, ldo8, ldo9, ldo10, and ldo11 are set through serial interface but ldo7 and ldo9 are gated (and gate) with sleep- signal, in order to get into sleep mode. if the sleep- signal is enabled (goes ?low?), the outputs of ldo7 and ldo9 are turned off. remainder of ldos as ldo1, ldo2, and ldo6 is controlled by ?power on logic?. a sub ldo called ?ldo3b? is independent control and this ldo control block doesn?t control ldo3b. and main ldo3 called ?ldo3a? is turned on by power_on signal, but sub ldo3 called ?ldo3b? is always on while battery supplies and ldo3b is only controlled by ddlo. a ddlo is control signal from battery charger block and is monitoring battery voltage. when vbat is under 2.5v (200mv hysteresis from vbat=2.7v), ddlo minimizes (ddlo enable) current flow from li-ion battery. main ldos : ldo1a, ldo2a, ldo3a, ldo6a sub ldos : ldo1b, ldo2b, ldo3b, ldo6b table 4a. ddlo status table status ldo1a ldo1b ldo2a ldo2b ldo3a ldo3b ldo4 refo ldo5 ldo6a ldo6b ldo7 ldo8 ldo9 ldo10 ldo11 baseband vdd baseband avdd coin cell audio refo vibrator baseband core rx1 tx rx2 rf option option ddlo enable off off off off off off off off off off off off off off off off ddlo disable xxxxxonxx x x xxxxxx note ADP3500 rev.prp 2 /6/02 - 23 - 1. ?x? means a status of ldo depends on other conditions. table 4b. ldo control event table event ldo1a ldo1b ldo2a ldo2b ldo3a ldo3b ldo4 refo ldo5 ldo6a ldo6b ldo7 ldo8 ldo9 ldo10 ldo11 baseband vdd baseband avdd coin cell audio refo vibrator baseband core rx1 tx rx2 rf option option power on (note 2) on on on on on on on tcxo_on (note 3) on/ off on/ off on/ off on/ off sleep- (note 4) on/ off on/ off resetin- off off off off off off off off ?alloff? bit goes ?h? off off off off off off off off ?pwroff? bit goes ?h? off off off off off off off off off off off off off off off notes 1. this table only indicate the change of status caused by an event. blank cells means ?no change? and keep previous status 2. power on event: indicating a status just after the power on event. after the event, a status of ldo1a, 2a, 3a, and ldo6a are changed by tcxo_on signal. 3. tcxo_on: hardware control, change all main-ldo? on/off status. 4. sleep-: the ldo7 and ldo9 are able to be controlled by software if sleep=?h? level. if sleep- goes ?l?, these ldos are turned off immediately. table 4c. software controllability of ldos ldo1a ldo1b ldo2a ldo2b ldo3a ldo3b ldo4 refo ldo5 ldo6a ldo6b ldo7 ldo8 ldo9 ldo10 ldo11 ldo description baseband vdd baseband avdd coin cell audio refo vibrator baseband core rx1 tx rx2 rf option option software turn on ? (note1) (note1) ? software turn off ???? ? ?????? note 1. ldo7 and ldo9 have a gate with sleep-. if sleep- is in ?l? (active) status, user cannot control and both ldos are kept to ?off? status. user may want to use this function as immediate control to get off status by using sleep- hardware control while set register ?1? to the ldo control register. 2.9 rtc block the calendar registers are set through serial interface. 2.9.1 function ? rtc counter using binary ? reading out and writing setting s of year, month, day, week, hour, minute, and second data. ? leap year controls, number of days in a month control ? alarm function (weak, hour, minute) ? periodic interrupt function - 2hz, 1hz, 1/60hz, 1/3600hz, each month (first day of each month) ? protection of wrong data readout during rtc data update. ADP3500 rev.prp 2 /6/02 - 24 - usec counter rtc counter loading alarm times rtc_write_enable rtc_clk32k rtc_data[7:0] rtc_alarm_int rtc_cs rtc_ctfg_int rtc_write_data[7:0] (from serial i/f) rtc register block rtc_sp_addr[5:0] alarm comparator periodic interrupt data select leap year and date control reset will be asserted when rtc counter is writed. registers for test mode - reset to rtc & usec counters - write initial d ata of usec counter sec counter increment control figure 15. rtc counter block 2.9.2 operation synchronizing with rtc_clk32k clock, usec counter generates 1sec timing clock and the clock hits rtc counter. through the serial interface, cpu can write setting value and read rtc counter value. in case the rtc counter toggles during the serial interface access to rtc counter, the wrong data can be read/write between rtc counter and interface. cs signal stops the clocking to rtc counter until cs signal is released. in case cpu writes data into sec counter, usec counter is reset to zero. note ? in case of rtc counter access, the access should be waited approximately 62 s, (2 clock cycles of clk32k) after the cs signal is asserted, to hold the rtc value. ? cs signal should never be asserted 1sec or longer, this affects counter operation. 2.9.3 operation of usec counter usec counter counts up synchronizing with rtc_clk32k clock. it generates 1sec timing signal and it is used as an increment clocking of rtc counter. in case the 1sec signal is generated during cs signal asserted, the increment clock is delayed until cs signal is released. 2.9.4 operation of rtc counter rtc counter uses the increment signal from usec counter to control counting operation including the leap year control and numbers of days in a month control. ADP3500 rev.prp 2 /6/02 - 25 - addr06h_write usec counter addr00h_write 7 scale 31 scale 12 scale 100 scale 00h 01h 02h 03h 04h 05h 06h month_count year_count day_count hour_count week_count min_count sec_count enabled signals created by decoding of rtc_sp_addr[5:0] initial data 12 scale 60 scale 60 scale leap year & days in month control inc_enb inc_clk to following counters year month date week hour minute second figure 16. rtc counter block diagram definition of leap year the definition of a leap year is, ?a year which can be divided by 4 and can not be divided by 100? and ?a year which can be divided by 400.? for this device, the following definition is used instead. ?a year which can be divided by 4? note - year counter = ?00? means year 2000, and is a leap year because it can be divided by 400. - actual covered year period is from 1901 to 2099. number of days of month control months 1, 3, 5, 7, 8, 10, 12 have 31days. months 4, 6, 9, 11 have 30days. month 2 has 28days, but has 29 in leap year. 2.9.5 alarm function comparing the rtc counter value with the seting value in alarm_setting register (07h-09h), alarm condition is detected. setting of week uses 7bits for each day in a week, and works with multiple days setting. there is a delay of 62 sfromalarm detection to setting up to aout/bout registers. ala_en flag in alarm control register (0dh) sets enable/disable of alarm detection. int register (1eh) indicates the interrupt signals, alarm_int of ala or/and alb. int mask register (1fh) do mask of alarm interrupt signal. alarm detection state is indicated as aout of alarm control register (0dh), and the alarm can be released by writing ?1? at the bit. alarm b is also controlled as same as alarm a is. note: user just need to write ?1? to release the alarm, and not need to write ?0? after ?1?. user doesn?t need to wait 62 s from cs assertion. 2.9.6 periodic interrupt function this is a function, which generates interrupt periodically. the timing of cycle can be selected from 2hz (0.5sec clock pulse), 1hz (1sec clock pulse), 1/60hz (minutes), 1/3600hz (hour), and month (first day of each month). the cycle is set using ct2-ct0 value in ctfg control register (0eh). the state when interrupt is generated is indicated at intra bit of ctfg control register (0eh). int mask register (1fh) only does mask of periodic interrupt signal. there are two kinds of pattern of ctfg interrupt signal output. ? hold the value when the interrupt is occurred (level). ? after the interrupt event is happened, assert interrupt signal in certain time period then release it (pulse). ADP3500 rev.prp 2 /6/02 - 26 - in level case, interrupt is occurred at each 0 min (1/60hz), 0 o?clock (1/3600hz) or at first day of month. because they are happened in long cycle, the value is held at register. after the cpu checks the state, it is released by writing ?1? at ctfg bit of ctfg control register. in case of 2hz and 1hz, the interrupt is not held because the event happens in short cycle. these event signal output pulse signal of 2hz or 1hz in rtc counter directly. interrupt release operation doesn?t affect on the interrupt signal in the case. 2.10 stay-alive timer this is a counter, which increments each 250ms after rtc_resetin_n is asserted. i t holds its value when the counter counts full up. signal clk4 is a 4hz (250ms) clock which generated in usec counter. the counter can be reset by writing ?1? at clr of stay-alive timer control register (0fh). the rtc_resetin_n signal is transferred from a logic input circuit, that is supplied by vbat, of resetin_n. note : user just need to write ?1? to release the interrupt, and not need to write ?0? after ?1?. 5bit counter test_reset clk4 clrb d sa[4:0] rtc_resetin_n register stay-alive timer stay-alive timer control register (0fh): clr stay-alive timer control register (0fh): sax figure 17. stay-alive timer block diagram clk4 sa_count[4:0] sa_clear 3210 431 530 0 rtc_voltage_detect figure 18. stay-alive timer operation timing ADP3500 rev.prp 2 /6/02 - 27 - 2.11 registers addr description d7 d6 d5 d4 d3 d2 d1 d0 comment 00h sec. counter s5 s4 s3 s2 s1 s0 note 1,5 01h min. counter m5 m4 m3 m2 m1 m0 note 1,5 02h hour counter h4 h3 h2 h1 h0 note 1,5 03h week counter w2 w1 w0 note 1,5 04h day counter d4 d3 d2 d1 d0 note 1,5 05h month counter mo3 mo2 mo1 mo0 note 1,5 06h year counter y6 y5 y4 y3 y2 y1 y0 note 1,5 07h alarm_a min register am5 am4 am3 am2 am1 am0 note 5 08h alarm_a hour register ah4 ah3 ah2 ah1 ah0 note 5 09h alarm_a week register aw6 aw5 aw4 aw3 aw2 aw1 aw0 note 5 0ah alarm_b min register bm5 bm4 bm3 bm2 bm1 bm0 note 5 0bh alarm_b hour register bh4 bh3 bh2 bh1 bh0 note 5 0ch alarm_b week register (option) bw6 bw5 bw4 bw3 bw2 bw1 bw0 note 5 0dh alarm control ala_en aout alb_en bout note 5 0eh periodic interrupt control ctfg ct2 ct1 ct0 note 5 0fh stay-alive timer control clr sa4 sa3 sa2 sa1 sa0 note 5 10h charger control chi chen note 4 11h charger mvbat control ref0 mven note 4 12h charger mvbat chv1 chv0 mv4 mv3 mv2 mv1 mv0 note 4 13h ldo control 1 ldo11 ldo5 ldo4 note 4 14h not available note 7 15h ldo control 2 ldo10 ldo9 ldo8 ldo7 note 4 16h ldo control 3 allof f note 4 17h ldo2 gain g23 g22 g21 g20 note 4 18h keypad column/b-light register bl ko3 ko2 ko1 ko0 note 6 19h keypad row ki5 ki4 ki3 ki2 ki1 ki0 note 6 1ah gpio control register gpc3 gpc2 gpc1 gpc0 note 6 1bh gpio mask gpmsk3 gpmsk2 gpmsk1 gpmsk 0 note 6 1ch gpio register gpi3 gpo3 gpi2 gpo2 gpi1 gpo1 gpi0 gpo0 note 6 1dh gpio int gpint3 gprst3 gpint2 gprst2 gpint1 gprst1 gpint0 gprst0 note 2,6 1eh int register in t7 ir st 7 int6 irst6 int5 int4 int3 irst3 int2 irst2 int1 irst1 int0 irst0 note 2,6 1fh int mask ms k7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 note 6 20h data in di6 di5 di4 di3 di2 di1 di0 note 6 21h power off pwrof f note 6 3fh test register (option) ldoenb usenb test note 3,5 notes: 1. for the rtc counter data protection, the access should be waited for certain time (62 s) period after cs signal assertion. (refer to rtc counter section for the wait time). 2. the int reset operation will be valid at 62 s or later after its setting. 3. this is a set register for internal test, and should not be accessed at normal operation. 4. analog block control registers. they control ldo etc. they are powered by vbat. 5. registers regarding rtc counter. they are powered by rtcv. 6. registers for int, gpio, keypad i/f etc. they are powered by vbat. 7. not available. ADP3500 rev.prp 2 /6/02 - 28 - typical performance characteristics (vin=4.2v,ta=25c) 2.900 2.905 2.910 2.915 2.920 2.925 0 5 0 100 150 output current, ma output voltage, v 2.876 2.877 2.877 2.878 2.878 2.879 2.879 0 0.2 0.4 0.6 0.8 1 output current, ma output voltage, v tpc1, ldo1a load regulation tpc2, ldo1b load regulation 2.860 2.862 2.864 2.866 2.868 2.870 2.872 0 1020304050 output current, ma output voltage, v 2.811 2.812 2.812 2.812 2.812 2.812 2.813 2.813 2.813 0 0 .05 0 .1 0.15 0.2 0 .25 0 .3 0.35 output current, ma output voltage, v tpc3, ldo6a load regulation tpc4, ldo6b load regulation 2.885 2.890 2.895 2.900 2.905 2.910 2.915 2.920 0 5 0 100 150 200 output current, ma output voltage, v 2.885 2.890 2.895 2.900 2.905 2.910 2.915 2.920 0 5 0 100 150 200 output current, ma output voltage, v tpc5, ldo4 load regulation tpc6, ldo7 load regulation ADP3500 rev.prp 2 /6/02 - 29 - package dimension 0.063 (1.60) max seating plane 0.003 (0.008) max lead coplanarity 0.030 (0.75) 0.024 (0.60) 0.018 (0.45) 7 8 0 8 0.057 (1.45) 0.055 (1.40) 0.053 (1.35) 0.006 (0.15) 0.002 (0.05) top view (pins dow n) 1 16 17 33 32 48 49 64 0.016 (0.4) bsc 0.354 (9.00) bsc sq 0.276 (7.00) bsc sq 0.009 (0.23) 0.007 (0.18) 0.005 (0.13) controlling dimensions are in millimeters st-64a 64-lead thin plastic quad flatpack [lqfp] 7 x 7mm body, 1.4mm thick |
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